PSD913F2 datasheet(33/91 Pages) STMICROELECTRONICS

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PSD9XX Family

PSD935G2

The

PSD935G2

Functional

Blocks

(cont.)

9.2 PLDs

The PLDs bring programmable logic functionality to the PSD935G2. After specifying the

logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon

power-up.

The PSD935G2 contains two PLDs: the Decode PLD (DPLD), and the General Purpose

PLD (GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more

detail in sections 9.2.1 and 9.2.2. Figure 11 shows the configuration of the PLDs.

The DPLD performs address decoding for internal components, such as memory,

registers, and I/O port selects.

The GPLD can be used to generate external chip selects, control signals or logic functions.

The GPLD has 24 outputs that are connected to Port A, B and C.

The AND array is used to form product terms. These product terms are specified using

PSDsoft. An Input Bus consisting of 66 signals is connected to the PLDs. The signals are

shown in Table 12. The complement of the 66 signals are also available as inputs to the

AND array.

Input Source

Input Name

Number

of Signals

MCU Address Bus

A[15:0]

MCU Control Signals

CNTL[2:0]

Reset

RST

Power Down

PDN

Port A Input

PA[7-0]

Port B Input

PB[7-0]

Port C Input

PC[7-0]

Port D Inputs

PD[3:0]

Port F Inputs

PF[7:0]

Page Register

PGR(7:0)

Flash Programming Status Bit

Rdy/Bsy

Table 12. DPLD and GPLD Inputs

NOTE: The address inputs are A[19:4] in 80C51XA mode.

The Turbo Bit

The PLDs in the PSD935G2 can minimize power consumption by switching to standby

when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo

mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if

no inputs are changing. Turbo-off mode increases propagation delays while reducing

power consumption. Refer to the Power Management Unit section on how to set the Turbo

Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals

from entering the PLDs. This reduces power consumption and can be used only when

these MCU control signals are not used in PLD logic equations.

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