STM8L151C4 datasheet(91/101 Pages) STMICROELECTRONICS

91 / 101 page

STM8L151xx, STM8L152xx

Electrical parameters

Doc ID 15962 Rev 2

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Static latch-up

●

LU: 3 complementary static tests are required on 10 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current

injection (applied to each input, output and configurable I/O pin) are performed on each

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to the application note AN1181.

8.4

Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table 15: General operating conditions on page 58.

The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using

the following equation:

TJmax = TAmax + (PDmax x ΘJA)

Where:

●

TAmax is the maximum ambient temperature in ° C

●

ΘJA is the package junction-to-ambient thermal resistance in ° C/W

●

PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)

●

PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip

internal power.

●

PI/Omax represents the maximum power dissipation on output pins

Where:

PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),

taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in

the application.

Table 50.

ESD absolute maximum ratings

Symbol

Ratings

Conditions

Maximum

value (1)

Data based on characterization results, not tested in production.

Unit

VESD(HBM)

Electrostatic discharge voltage

(human body model)

TA = +25 °C

2000

VESD(CDM)

Electrostatic discharge voltage

(charge device model)

1000

Table 51.

Electrical sensitivities

Symbol

Parameter

Class

Static latch-up class

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