ATtiny5 datasheet(67/168 Pages) ATMEL

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8127C–AVR–10/09

ATtiny4/5/9/10

Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x.

Note that when using fixed TOP values, the unused bits are masked to zero when any of the

OCR0x Registers are written. As the third period shown in Figure 11-10 on page 66 illustrates,

changing the TOP actively while the Timer/Counter is running in the phase correct mode can

result in an unsymmetrical output. The reason for this can be found in the time of update of the

OCR0x Register. Since the OCR0x update occurs at TOP, the PWM period starts and ends at

TOP. This implies that the length of the falling slope is determined by the previous TOP value,

while the length of the rising slope is determined by the new TOP value. When these two values

differ the two slopes of the period will differ in length. The difference in length gives the unsym-

metrical result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct

mode when changing the TOP value while the Timer/Counter is running. When using a static

TOP value there are practically no differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COM0x1:0 to three (See Table 11-4 on page 74).

The actual OC0x value will only be visible on the port pin if the data direction for the port pin is

set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x

clearing (or setting) the OC0x Register at compare match between OCR0x and TCNT0 when

the counter decrements. The PWM frequency for the output when using phase correct PWM can

be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR0x Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

11.8.5

Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM

mode (WGM03:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-

form generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the

Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while

upcounting, and set on the compare match while downcounting. In inverting Compare Output

mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-

quency compared to the single-slope operation. However, due to the symmetric feature of the

dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCR0x Register is updated by the OCR0x Buffer Register, (see Figure 11-

10 on page 66 and Figure 11-11 on page 68).

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and

fOCnxPCPWM

fclk_I/O

2N TOP

⋅⋅

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