ATtiny5 datasheet(68/168 Pages) ATMEL

68 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can

be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICR0 (WGM03:0 = 8), or the value in OCR0A (WGM03:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNT0 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 11-11 on page 68. The figure shows phase and fre-

quency correct PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in

the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0

slopes represent compare matches between OCR0x and TCNT0. The OC0x interrupt flag will be

set when a compare match occurs.

Figure 11-11. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x

Registers are updated with the double buffer value (at BOTTOM). When either OCR0A or ICR0

is used for defining the TOP value, the OC0A or ICF0 flag set when TCNT0 has reached TOP.

The interrupt flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x.

As Figure 11-11 on page 68 shows the output generated is, in contrast to the phase correct

mode, symmetrical in all periods. Since the OCR0x Registers are updated at BOTTOM, the

length of the rising and the falling slopes will always be equal. This gives symmetrical output

pulses and is therefore frequency correct.

RPFCPWM

TOP 1

()

log

()

log

-----------------------------------

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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