ATtiny5 datasheet(41/168 Pages) ATMEL

41 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 10-2. General Digital I/O(1)

Note:

1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port.

clkI/O, and SLEEP are common to all ports.

10.2.1

Configuring the Pin

Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in

“Register Description” on page 50, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, the PUExn bits at the PUEx I/O address, and the PINxn

bits at the PINx I/O address.

clk

RPx

RRx

RDx

WDx

WEx

SYNCHRONIZER

WDx:

WRITE DDRx

WRx:

WRITE PORTx

RRx:

READ PORTx REGISTER

RPx:

READ PORTx PIN

clk

I/O:

I/O CLOCK

RDx:

READ DDRx

WEx:

WRITE PUEx

REx:

READ PUEx

REx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

SLEEP

SLEEP:

SLEEP CONTROL

Pxn

I/O

WPx

RESET

CLR

PUExn

WRx

WPx:

WRITE PINx REGISTER

ATtiny5 数据表(PDF) 41 Page - ATMEL Corporation

ATtiny5 数据表(HTML) 41 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载