ATtiny5 datasheet(69/168 Pages) ATMEL

69 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using

ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However,

if the base PWM frequency is actively changed by changing the TOP value, using the OCR0A as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-

forms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and

an inverted PWM output can be generated by setting the COM0x1:0 to three (See Table 11-4 on

page 74). The actual OC0x value will only be visible on the port pin if the data direction for the

port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing)

the OC0x Register at the compare match between OCR0x and TCNT0 when the counter incre-

ments, and clearing (or setting) the OC0x Register at compare match between OCR0x and

TCNT0 when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR0x Register represents special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be set to high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

11.9 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set, and when the OCR0x Register is updated with the OCR0x buffer value (only for

modes utilizing double buffering). Figure 11-12 on page 69 shows a timing diagram for the set-

ting of OCF0x.

Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, no Prescaling

fOCnxPFCPWM

fclk_I/O

2NTOP

⋅⋅

-----------------------------

clk

(clk

I/O/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

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