ATtiny5 datasheet(60/168 Pages) ATMEL

60 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

double buffering is disabled. The double buffering synchronizes the update of the OCR0x Com-

pare Register to either TOP or BOTTOM of the counting sequence. The synchronization

prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-

put glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR0x directly. The content of the OCR0x (Buffer or Compare)

automatically as the TCNT0 and ICR0 Register). Therefore OCR0x is not read via the high byte

temporary register (TEMP). However, it is a good practice to read the low byte first as when

accessing other 16-bit registers. Writing the OCR0x Registers must be done via the TEMP Reg-

ister since the compare of all 16 bits is done continuously. The high byte (OCR0xH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCR0xL) is written to the lower eight bits,

the high byte will be copied into the upper 8-bits of either the OCR0x buffer or OCR0x Compare

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 71.

11.6.1

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (0x) bit. Forcing compare match will not set the

OCF0x flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare

match had occurred (the COM01:0 bits settings define whether the OC0x pin is set, cleared or

toggled).

11.6.2

Compare Match Blocking by TCNT0 Write

All CPU writes to the TCNT0 Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the

same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled.

11.6.3

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using any of the Output Compare

channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect wave-

form generation. Do not write the TCNT0 equal to TOP in PWM modes with variable TOP

values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.

Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting.

The setup of the OC0x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-

pare (0x) strobe bits in Normal mode. The OC0x Register keeps its value even when changing

between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value.

Changing the COM0x1:0 bits will take effect immediately.

ATtiny5 数据表(PDF) 60 Page - ATMEL Corporation

ATtiny5 数据表(HTML) 60 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载