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ATtiny5 数据表(PDF) 77 Page - ATMEL Corporation |
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ATtiny5 数据表(HTML) 77 Page - ATMEL Corporation |
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77 / 168 page  77 8127C–AVR–10/09 ATtiny4/5/9/10 The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that the FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the COM0x1:0 bits that determine the effect of the forced compare. A FOC0A/FOC0B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR0A as TOP. The FOC0A/FOC0B bits are always read as zero. • Bits 5:0 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when the register is written. 11.11.4 TCNT0H and TCNT0L – Timer/Counter0 The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 71. Modifying the counter (TCNT0) while the counter is running introduces a risk of missing a com- pare match between TCNT0 and one of the OCR0x Registers. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock for all compare units. 11.11.5 OCR0AH and OCR0AL – Output Compare Register 0 A 11.11.6 OCR0BH and OCR0BL – Output Compare Register 0 B The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an Bit 765 432 10 0x29 TCNT0[15:8] TCNT0H 0x28 TCNT0[7:0] TCNT0L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 0x27 OCR1A[15:8] OCR0AH 0x26 OCR1A[7:0] OCR0AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 0x25 OCR0B[15:8] OCR0BH 0x24 OCR0B[7:0] OCR0BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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