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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ATtiny5 数据表(PDF) 70 Page - ATMEL Corporation |
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ATtiny5 数据表(HTML) 70 Page - ATMEL Corporation |
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70 / 168 page  70 8127C–AVR–10/09 ATtiny4/5/9/10 Figure 11-13 on page 70 shows the same timing data, but with the prescaler enabled. Figure 11-13. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) Figure 11-14 on page 70 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR0x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV0 flag at BOTTOM. Figure 11-14. Timer/Counter Timing Diagram, no Prescaling Figure 11-15 on page 71 shows the same timing data, but with the prescaler enabled. OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk Tn (clk I/O/1) clk I/O |
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