ATtiny5 datasheet(64/168 Pages) ATMEL

64 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor-

rect and phase and frequency correct PWM modes that use dual-slope operation. This high

frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or

OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the max-

imum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can be

calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGM03:0 = 5, 6, or 7), the value in ICR0 (WGM03:0 =

14), or the value in OCR0A (WGM03:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-9 on page 64. The

figure shows fast PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is

in the timing diagram shown as a histogram for illustrating the single-slope operation. The dia-

gram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the

TCNT0 slopes represent compare matches between OCR0x and TCNT0. The OC0x interrupt

flag will be set when a compare match occurs.

Figure 11-9. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. In addition

the OC0A or ICF0 flag is set at the same timer clock cycle as TOV0 is set when either OCR0A or

ICR0 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCR0x Registers are written.

RFPWM

TOP 1

()

log

()

log

-----------------------------------

TCNTn

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

ATtiny5 数据表(PDF) 64 Page - ATMEL Corporation

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