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MPC8536EBVTATH 数据表(PDF) 106 Page - Freescale Semiconductor, Inc |
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MPC8536EBVTATH 数据表(HTML) 106 Page - Freescale Semiconductor, Inc |
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106 / 128 page  MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Clocking Freescale Semiconductor 106 NOTE The reference impedance for return loss measurements is 50. to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50. probes—see Figure 71). Note that the series capacitors, CTX, are optional for the return loss measurement. Figure 70. Minimum Receiver Eye Timing and Voltage Compliance Specification 2.22.0.1 Compliance Test and Measurement Load The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 71. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. Figure 71. Compliance Test/Measurement Load 2.23 Clocking This section describes the PLL configuration of the MPC8536E. Note that the platform clock is identical to the core complex bus (CCB) clock. |
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