MPC8536EBVTATH datasheet(109/128 Pages) FREESCALE

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Clocking

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

109

Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.

The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down

mode where the DDR bus clock is half the speed of the default configuration. Changing of these defaults must be completed

prior to initialization of the DDR controller.

2.23.5

PCI Clocks

The integrated PCI controller in MPC8536E supports PCI input clock frequency in the range of 33–66 MHz. The PCI input

clock can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the

PCI1_CLK, refer to the PCI 2.2 Specification.

The use of PCI1_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of

PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.

Table 77. DDR Clock Ratio

Functional Signals

Reset Configuration

Name

Value (Binary)

DDR:DDRCLK Ratio

TSEC_1588_TRIG_OUT[0:1],

TSEC1_1588_CLK_OUT

cfg_ddr_pll[0:2]

000

3:1

001

4:1

010

6:1

011

8:1

100

10:1

101

12:1

110

Reserved

111

Synchronous mode

MPC8536EBVTATH 数据表(PDF) 109 Page - Freescale Semiconductor, Inc

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