MPC8536EBVTATH datasheet(114/128 Pages) FREESCALE

114 / 128 page

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

System Clocking

Freescale Semiconductor

114

Figure 74 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.

Figure 74. Package with Heat Sink Mounted to a Printed-Circuit Board

The heat sink removes most of the heat from the device for most applications. Heat generated on the active side of the chip is

conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat

sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance

are the dominant terms.

2.24.3.2

Thermal Interface Materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The

performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is

generally provided by the thermal interface vendors.

Hardware Design Considerations

This section provides electrical and thermal design recommendations for successful application of the MPC8536E.

3.1

System Clocking

This device includes seven PLLs:

•

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio

between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in

Section 2.23.2, “CCB/SYSCLK PLL Ratio.”

•

The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500

core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 2.23.3,

“e500 Core PLL Ratio/”

•

The PCI PLL generates the clocking for the PCI bus

•

The local bus PLL generates the clock for the local bus.

•

There is a PLL for the SerDes1 block to be used for PCI Express interface

•

There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces.

•

The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The

frequency ratio between the DDR clock and DDRCLK is described in Section 2.23.4, “DDR/DDRCLK PLL Ratio.”

External Resistance

Internal Resistance

Radiation

Convection

Radiation

Convection

Heat Sink

Printed-Circuit Board

Thermal Interface Material

Package/Solder Spheres

Die Junction

Die/Package

(Note the internal versus external package resistance)

MPC8536EBVTATH 数据表(PDF) 114 Page - Freescale Semiconductor, Inc

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