MPC8536EBVTATH datasheet(119/128 Pages) FREESCALE

119 / 128 page

JTAG Configuration Signals

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

119

The COP interface has a standard header, shown in Figure 79, for connection to the target system, and is based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a

connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and

other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.

There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from

emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while

still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement

recommended in Figure 79 is common to all known emulators.

3.10.1

Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

•TRST should be tied to HRESET through a 0 k

Ω isolation resistor so that it is asserted when the system reset signal

(HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale

recommends that the COP header be designed into the system as shown in Figure 78. If this is not possible, the

isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in

future debug situations.

•

No pull-up/pull-down is required for TDI, TMS, or TDO.

MPC8536EBVTATH 数据表(PDF) 119 Page - Freescale Semiconductor, Inc