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MPC8536EBVTATH 数据表(PDF) 121 Page - Freescale Semiconductor, Inc |
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MPC8536EBVTATH 数据表(HTML) 121 Page - Freescale Semiconductor, Inc |
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121 / 128 page  Guidelines for High-Speed Interface Termination MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 121 Figure 79. COP Connector Physical Pinout 3.11 Guidelines for High-Speed Interface Termination 3.11.1 SerDes1 Interface Entirely Unused If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However, the SerDes must always have power applied to its supply pins. See SerDes1 in Table 1 for details. The following pins must be left unconnected (float): • SD1_TX[7:0] • SD1_TX[7:0] • Reserved pins T22, T23 The following pins must be connected to XGND: • SD1_RX[7:0] • SD1_RX[7:0] • SD1_REF_CLK • SD1_REF_CLK The POR configuration pin cfg_io_ports[0:2] on TSEC3_TXD[6:3] can be used to power down SerDes 1 block for power saving. Note that both SVDD and XVDD must remain powered. 3.11.2 SerDes 1 Interface Partly Unused If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float) if not used: • SD1_TX[7:0] • SD1_TX[7:0] • Reserved pins: T22, T23 3 13 9 5 1 6 10 15 11 7 16 12 8 4 KEY No pin 1 2 COP_TDO COP_TDI NC NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC GND COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CHKSTP_OUT |
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