CS49310 datasheet(46/90 Pages) CIRRUS

46 / 90 page

CS49300 Family DSP

DS339F7

6.2.1. Intel Parallel Host

Communication Mode

The Intel parallel host communication mode is

implemented using the pins given in Table 6.

The INTREQ pin is controlled by the application

code when a parallel host communication mode

has been selected. When the code supports

INTREQ notification, the INTREQ pin is asserted

whenever the DSP has an outgoing message for

the host. This same information is reflected by the

HOUTRDY bit of the Host Control Register (A[1:0]

= 01b).

INTREQ is useful for informing the host of

unsolicited messages. An unsolicited message is

defined as a message generated by the DSP

without

associated

host

read

request.

Unsolicited messages can be used to notify the

host of conditions such as a change in the

incoming audio data type (e.g. PCM --> AC-3).

6.2.1.1. Writing a Byte in Intel Mode

Information provided in this section is intended as

a functional description of how to write control

information to the CS493XX. The system designer

must insure that all of the timing constraints of the

Intel Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 24 illustrates the

sequence of events that define a one-byte write in

Intel mode. The protocol presented in Figure 24

will now be described in detail.

1) The host must first drive the A1 and A0 register

address pins of the CS493XX with the address

of the desired Parallel I/O Register.

Host Message:

A[1:0]==00b.

Host Control:

A[1:0]==01b.

PCMDATA:

A[1:0]==10b.

CMPDATA:

A[1:0]==11b.

2) The host then indicates that the selected

cycle by driving the CS and WR pins low.

3) The host drives the data byte to the DATA[7:0]

pins of the CS493XX.

4) Once the setup time for the write has been met,

the host ends the write cycle by driving the CS

and WR pins high.

6.2.1.2. Reading a Byte in Intel Mode

Information provided in this section is intended as

a functional description of how to write control

information to the CS493XX. The system designer

must insure that all of the timing constraints of the

Intel Parallel Host Mode Read Cycle are met.

Mnemonic

Pin Name

Pin Number

Chip Select

Write Enable

Output Enable

Interrupt Request

INTREQ

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Table 6. Intel Mode Communication Signals

ADDRESS A PARALLEL I/O REGISTER

CS (LOW)

WRITE BYTE TO

CS (HIGH)

WR (LOW)

(A[1:0] SET APPROPRIATELY

DATA [7:0]

WR (HIGH)

Figure 24. Intel Mode, One-Byte Write Flow Dia-

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