CS49310 datasheet(72/90 Pages) CIRRUS

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CS49300 Family DSP

DS339F7

10.5. Digital Audio Output Port

The Digital Audio Output port, or DAO, is the port

used for digital output from the DSP. Table 15

shows the signals associated with the DAO. As

with the input ports the clocks and data are fully

configurable via hardware configuration.

MCLK is the master clock and is firmware

configurable to be either an input or an output. If

MCLK is to be used as an output, the internal PLL

must be used. As an output MCLK can be

configured to provide a 128Fs, 256Fs or 512Fs

clock, where Fs is the output sample rate.

SCLK is the bit clock used to clock data out on

AUDATA0, AUDATA1, AUDATA2 and AUDATA3.

LRCLK is the data framing clock whose frequency

is typically equal to the sampling frequency. Both

LRCLK and SCLK can be configured as either

inputs (Slave mode) or outputs (Master mode).

When LRCLK and SCLK are configured as inputs,

MCLK is a don’t care as an input. When LRCLK

and SCLK are configured as outputs, they are

derived from MCLK. Whether MCLK is configured

as an input or an output, an internal divider from

the MCLK signal is used to produce LRCLK and

SCLK. The ratios shown in Table 16 give the

possible

SCLK

values

for

different

MCLK

frequencies (all values in terms of the sampling

frequency, Fs).

AUDAT0 is configurable to provide six, four, or two

channels. AUDATA1, AUDATA2 and AUDATA3

can both output two channels of data. Typically the

AUDATA0, AUDATA1, AUDATA2 and AUDATA3

outputs are used in left justified, I2S or right

justified

modes.

AUDATA0,

AUDATA1

and

AUDATA2 are used for 5.1 output, presenting all

six channels of surround sound (Left, Center,

Right,

Left

Surround,

Right

Surround

and

Subwoofer).

AUDATA3 can be used with AUDATA0, AUDATA1

and AUDATA2 to support 7.1 output. Alternatively

AUDATA3 can be used for dual zone support.

AUDATA3 is multiplexed with the XMT958 output

so only one can be used at any one time.

Table 17 shows the mapping of DAO channels to

actual outputs when not in a multichannel mode.

Pin Name

Pin Description

Pin Number

AUDATA3,

XMT958

Serial Data Out

IEC60958 Transmitter

AUDATA2

Serial Data Out

AUDATA1

Serial Data Out

AUDATA0

Serial Data Out

LRCLK

Frame Clock

SCLK

Serial Bit Clock

MCLK

Master Clock

Table 15. Digital Audio Output Port

MCLK

(Fs)

SCLK (Fs)

128

256

512

128

384**

256

512

XXXX

** For MCLK as an input only

Table 16. MCLK/SCLK Master Mode Ratios

DAO_Channel

Subframe

Signal

Left

AUDATA0

Right

AUDATA0

Left

AUDATA1

Right

AUDATA1

Left

AUDATA2

Right

AUDATA2

Left

AUDATA3

Right

AUDATA3

Table 17. Output Channel Mapping

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