CS49310 datasheet(44/90 Pages) CIRRUS

44 / 90 page

CS49300 Family DSP

DS339F7

When using automated communication ports,

however, the host is often limited to sampling the

status of INTREQ after an entire byte has been

transferred.

this

situation

low-high-low

transition (case 3) would be missed and the host

will see a constantly low INTREQ pin. Since the

host should read from the CS493XX until it detects

that INTREQ has gone high, this condition will be

treated as a multiple-message read (more than

one read response is provided by the CS493XX).

Under these conditions a single byte of 0x00 will be

read out before the unsolicited message.

The length of every read response is defined in the

user’s manual for each piece of application code.

Thus, the host should know how many bytes to

expect based on the first byte (the OPCODE) of a

read response message. It is guaranteed that no

read responses will begin with 0x00, which means

that a NULL byte (0x00) detected in the OPCODE

position of a read response message should be

discarded. Please see an Application Code User’s

Guide for an explanation of the OPCODE.

It is important that the host be aware of the

presence of NULL bytes, or the communication

channel could become corrupted.

When case (3) occurs and the host issues a stop

condition before starting a new read cycle, the first

byte of the unsolicited message is loaded directly

into the shift register and 0x00 is never seen.

Alternatively, if case (3) occurs and the host

continues to read from the CS493XX without a

stop condition (a multiple message read), the 0x00

byte must be shifted out of the CS493XX before

the first byte of the unsolicited message can be

read.

In other words, if a system can only sample

INTREQ after an entire byte transfer the following

routine should be used if INTREQ is low after the

last byte of the message being read:

1) Read one byte

2) If the byte = 0x00 discard it and skip to step 3.

If the byte != 0x00 then it is the OPCODE for

the next message. For this case skip to step 4.

3) Read one more byte. This is the OPCODE for

the next message.

4) Read the rest of the message as indicated in

the previous sections.

6.2. Parallel Host Communication

The parallel host communication modes of the

CS493XX provide an 8-bit interface to the DSP. An

Intel-style parallel mode and a Motorola-style

parallel mode are supported. The host interface is

implemented using four communication registers

within the CS493XX as shown in Table 5, “Parallel

Input/Output Registers,” on page 45.

When the host is downloading code to the

CS493XX or configuring the application code,

control messages will be written to (and read from)

the Host Message register. The Host Control

determine when the CS493XX can accept another

byte of control data, and when the CS493XX has

an outgoing byte that may be read.

The PCM Data and Compressed Data registers

are used strictly for the transfer of audio data. The

host cannot read from these two registers. Audio

data written to registers 11b and 10b are

transferred directly to the internal FIFOs of the

CS493XX. When the level of the PCM FIFO

reaches the FIFO threshold level, the MFC bit of

the Host Control register will be set. When the level

of the Compressed Data FIFO reaches the FIFO

threshold level, the MFB bit of the Host Control

It is important to remember that the parallel host

interface requires the DATA[7:0] pins of the

CS493XX. The external memory interface also

requires the DATA[7:0] pins so the Parallel host

control modes can only be used if external memory

is not required.

A detailed description for each parallel host mode

will now be given. The following information will be

provided for the Intel mode and Motorola mode:

•

The pins of the CS493XX which must be used

for proper communication

•

Flow diagram and description for a parallel

byte write

•

Flow diagram and description for a parallel

byte read

The four registers of the CS493XX’s parallel host

mode are not used identically. The algorithm used

for communicating with each register will be given

CS49310 数据表(PDF) 44 Page - Cirrus Logic

CS49310 数据表(HTML) 44 Page - Cirrus Logic

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