CS49310 datasheet(71/90 Pages) CIRRUS

71 / 90 page

CS49300 Family DSP

DS339F7

delivering data. If using I2C or SPI control, then

parallel delivery can still be used using CMPCLK

and GPIO[7:0].

10.4.1.Parallel Delivery with Parallel

Control

If using the Intel or Motorola Parallel host interface

mode, the system designer can also choose to

deliver data through the byte wide parallel port.

The delivery mechanism is identical to that

discussed

Section

6.2,

“Parallel

Host

Communication” on page 44.

The compressed data input register (CMPDAT)

receives bytes of data when the host interface

writes to address 11b (A1 and A0 are both high).

The host should check level of the Compressed

Data FIFO before sending data. The CS493XX has

two means of indicating the Compressed Data

FIFO level. The MFB bit in the Host Control

FIFO level. The MFB bit remains low until the FIFO

threshold has been reached. The alternative is to

use the CMPREQ pin of the CS493XX. The

CMPREQ pin also remains low until the FIFO

threshold has been reached. The host has the

option of using either CMPREQ or the MFB bit.

Data should be delivered to the CS493XX in blocks

of data. Before each block is delivered, the host

should check the MFB bit (or the CMPREQ pin). If

the MFB bit (CMPREQ) is low, then the host can

deliver a block of data one byte at a time. If the

MFB bit (CMPREQ) is high, no more data should

be sent to the CS493XX. Once the MFB bit

(CMPREQ) has gone low again, the host may send

another block of compressed audio data.

During delivery of a block of data the FIFO

threshold should not be checked. In other words

the FIFO indicators are level sensitive and indicate

that a block can be delivered when they are low.

They may return high during the data delivery.

When this happens there is still room for the

remaining bytes of the block.

The PCM data input register (PCMDAT) receives

bytes of data when the host interface writes to

address 10b (A1 high, A0 low). The MFC bit in the

Host Control Register is an indicator of the PCM

FIFO level. The MFC bit remains low until the FIFO

threshold has been reached.

The PCMRST bit of the CONTROL register

provides

absolute

software/hardware

synchronization by initializing the input channel to

uniquely recognize the first write to the byte-wide

PCMDATA port. Toggling PCMRST high and low

informs the DSP that the next sample read from

the PCMDATA port is the first sample of the left

channel. In this fashion, the CS493XX can

translate successive byte writes into a variable

number of channels with a variable PCM sample

size. In the most simple case, the CS493XX can

receive stereo 8-bit PCM one byte at a time with

the internal DSP assigning the first 8-bit write (after

PCMRST) to the left channel and the second 8-bit

write to the right channel. For 24-bit PCM, it

assigns the first three 8-bit writes (after PCMRST)

to the left channel and the next three writes to the

right channel. Before starting PCM transfer, or to

initiate a new PCM transfer, the PCMRST bit must

be toggled as described above to insure data

integrity.

Data must be delivered to the CS493XX in blocks

of data. The block size is set through a hardware

configuration message. Before each block is

delivered, the host should check the MFC bit. If the

MFC bit is low, then the host can deliver a block of

data one byte at a time. If the MFC bit is high, no

more data should be sent to the CS493XX. Once

the MFC bit has gone low again, the host may send

another block of PCM audio data. The MFC bit is

FIFO level sensitive. In other words, it may change

during the transfer of a block. The host should

complete the block transfer and ignore the MFC bit

until the block transfer is complete.

10.4.2.Parallel Delivery with Serial

Control

When using I2C or SPI control, bytewide delivery of

data

can

still

achieved

using

SCLKN2(CMPCLK) and GPIO[8:0]. In this mode

the bytewide parallel data is clocked into the part

on the transition of CMPCLK.

In this mode CMPREQ can be used as the FIFO

threshold indicator. When CMPREQ is low it

means that the CS493XX can receive another

block of data.

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