CS49310 datasheet(47/90 Pages) CIRRUS

47 / 90 page

CS49300 Family DSP

DS339F7

The flow diagram shown in Figure 25 illustrates the

sequence of events that define a one-byte read in

Intel mode. The protocol presented in Figure 25

will now be described in detail.

1) The host must first drive the A1 and A0 register

address pins of the CS493XX with the address

of the desired Parallel I/O Register. Note that

only the Host Message register and the Host

Control register can be read.

Host Message: A[1:0]==00b.

Host Control:

A[1:0]==01b.

2) The host now indicates that the selected

cycle by driving the CS and RD pins low.

3) Once the data is valid, the host can read the

value of the selected register from the

DATA[7:0] pins of the CS493XX.

4) The host should now terminate the read cycle

by driving the CS and RD pins high.

6.2.2. Motorola Parallel Host

Communication Mode

The Motorola parallel host communication mode is

implemented using the pins given in Table 7. The

INTREQ pin is controlled by the application code

when a parallel host communication mode has

been selected. When the code supports INTREQ

notification, the INTREQ pin is asserted whenever

the DSP has an outgoing message for the host.

This

same

information

reflected

the

HOUTRDY bit of the Host Control Register (A[1:0]

= 01b).

INTREQ is useful for informing the host of

unsolicited messages. An unsolicited message is

defined as a message generated by the DSP

without

associated

host

read

request.

Unsolicited messages can be used to notify the

host of conditions such as a change in the

incoming audio data type (e.g. PCM --> AC-3)

6.2.2.1. Writing a Byte in Motorola Mode

Information provided in this section is intended as

a functional description of how to write control

information to the CS493XX. The system designer

must insure that all of the timing constraints of the

Motorola Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 26 illustrates the

sequence of events that define a one-byte write in

Motorola

mode.

The

protocol

presented

Figure 26 will now be described in detail.

1) The host must drive the A1 and A0 register

address pins of the CS493XX with the address

of the address of the desired Parallel I/O

Host Message:

A[1:0]==00b.

Host Control:

A[1:0]==01b.

PCMDATA:

A[1:0]==10b.

Figure 25. Intel Mode, One-Byte Read Flow Dia-

ADDRESS A PARALLEL I/O REGISTER

CS (LOW)

READ BYTE FROM

CS (HIGH)

RD (LOW)

(A[1:0] SET APPROPRIATELY

DATA [7:0]

RD (HIGH)

Mnemonic

Pin Name

Pin Number

Chip Select

Data Strobe

Read or Write Select

R/W

Interrupt Request

INTREQ

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Table 7. Motorola Mode Communication Signals

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