CS49310 datasheet(69/90 Pages) CIRRUS

69 / 90 page

CS49300 Family DSP

DS339F7

10. DIGITAL INPUT & OUTPUT

The CS493XX supports a wide variety of data input

and output mechanisms through various input and

output ports. Hardware availability is entirely

dependent on whether the software application

code being used supports the required mode. This

data sheet presents most of the modes available

with the CS493XX hardware. This does not mean

that all of the modes are available with any

particular

piece

application

code.

The

application code user’s guide for the particular

code

being

used

should

referenced

determine if a particular mode is supported. In

addition if a particular mode is desired that is not

presented,

please

contact

your

sales

representative as to its availability.

10.1. Digital Audio Formats

This subsection will describe some common audio

formats that the CS493XX supports. It should be

noted that the input ports use up to 24-bit PCM

resolution and 16-bit compressed data word

lengths. The output port of the CS493XX provides

up to 24-bit PCM resolution.

10.1.1.I2S

Figure 43, "I2S Format" on page 69 shows the I2S

format. For I2S, data is presented most significant

bit first, one SCLK delay after the transition of

LRCLK and is valid on the rising edge of SCLK. For

the I2S format, the left subframe is presented when

LRCLK is low and the right subframe is presented

when LRCLK is high. SCLK is required to run at a

frequency of 48Fs or greater on the input ports.

10.1.2.Left Justified

Figure 44 shows the left justified format with a

rising edge SCCLK. Data is presented most

significant bit first on the first SCLK after an LRCLK

transition and is valid on the rising edge of SCLK.

For the left justified format, the left subframe is

presented when LRCLK is high and the right

subframe is presented when LRCLK is low. The

left justified format can also be programmed for

data to be valid on the falling edge of SCLK. SCLK

is required to run at a frequency of 48Fs or greater

on the input ports.

10.1.3.Multichannel

Figure 45 shows the multichannel format. In this

format up to 6 channels of audio are presented on

one data line with M bits per channel. Channels 0,

2, and 4 are presented while the LRCLK is high

and channels 1, 3, 5 are presented while the

LRCLK is low. Data is valid on the rising edge of

SCLK and is presented most significant bit first. It

should be noted that in the multichannel modes the

SCLK rate must be greater than the number of bits

per channel multiplied by the number of channels.

In the example SCLK must be greater than M * 6.

Because each of the ports is fully configurable

(SCLK polarity, LRCLK polarity, Word Width,

SCLK Rate) not all modes have been presented.

LR C K

SC L K

SD AT A

MS B

LS B

Left

R ig ht

MS B

LS B

Figure 43. I2S Format

LR C K

SC L K

SD A T A

MS B

LS B

Le ft

R ig h t

MS B

LS B

MS B

Figure 44. Left Justified Format (Rising Edge Valid SCLK)

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