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CS49310 数据表(PDF) 20 Page - Cirrus Logic

部件名 CS49310
功能描述  Multi-Standard Audio Decoder Family
PDF  90 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS49310 数据表(HTML) 20 Page - Cirrus Logic

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CS49300 Family DSP
20
DS339F7
1.13. Switching Characteristics — Serial Bursty Data Input
(VA, VD[3:1] = 2.5 V
±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Notes: 1. CMPREQ signal is asynchronous to CLKIN and can change at any time relative to CLKIN.
Parameter
Symbol
Min
Max
Unit
Serial compressed data clock CMPCLK period
Tcmpclk
-27
MHz
CMPDAT setup before CMPCLK high
Tcmpsu
5-
ns
CMPDAT hold after CMPCLK high
Tcmphld
3-
ns
Delay from falling edge of CMPREQ to CMPCLK rising edge
Treqclk
0-
ns
Tcmpsu
Tcmpclk
Tcmphld
CMPREQ
CMPCLK
CMPDAT
Treqclk
Figure 10. Serial Compressed Data Timing



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