CS49310 datasheet(41/90 Pages) CIRRUS

41 / 90 page

CS49300 Family DSP

DS339F7

the host is valid on the rising edge of SCCLK

and data transitions occur on the falling edge of

SCCLK.

6) If INTREQ is still low after a byte transfer, an

acknowledge (SCDIO clocked low by SCCLK)

must be sent by the host to the CS493XX and

another byte should be clocked out of the

CS493XX. Please see the discussion below for

a complete description of INTREQ’s behavior.

7) When INTREQ has risen, a no acknowledge

should be sent by the host (SCDIO clocked

high by the host) to the CS493XX. This,

followed by an I2C® stop condition (SCDIO

raised, while SCCLK is high) signals an end of

read to the CS493XX.

Understanding the role of INTREQ is important for

successful communication. INTREQ is guaranteed

to remain low (once it has gone low), until the rising

edge of SCCLK for the last bit of the last byte to be

transferred out of the CS493XX (i.e. the rising

edge of SCCLK before the ACK SCCLK). If there

is no more data to be transferred, INTREQ will go

high at this point. After going high, INTREQ is

guaranteed to stay high until the next rising edge of

SCCLK (i.e. it will stay high until the rising edge of

SCCLK for the ACK/NACK bit). This end of transfer

condition signals the host to end the read

transaction by clocking the last data bit out of the

CS493XX and then sending a no acknowledge to

the CS493XX to signal that the read sequence is

over. At this point the host should send an I2C®

stop condition to complete the read sequence. If

INTREQ is still low after the rising edge of SCCLK

on the last data bit of the current byte, the host

should send an acknowledge and continue reading

data from the serial control port.

It should be noted that all data should be read out

of the serial control port during one cycle or a loss

of data will occur. In other words, all data should be

read out of the chip until INTREQ signals the last

byte by going high as described above. Please see

Section 6.1.3, “INTREQ Behavior: A Special Case”

on page 41 for a more detailed description of

INTREQ behavior.

The timing diagram in Figure 24, "I2C® Timing" on

page 42 shows the relative edges of the control

lines for an I2C® read and write.

6.1.3. INTREQ Behavior: A Special

Case

When communicating with the CS493XX there are

two types of messages which force INTREQ to go

low. These messages are known as solicited

messages and unsolicited messages. For more

information on the specific types of messages that

require a read from the host, one of the application

code user’s guides should be referenced.

INTREQ LOW?

YES

SEND I2C START:

DROP SCDIO LOW

WHILE SCCLK IS HIGH

WRITE ADDRESS BYTE

SET TO 1 FOR READ

WITH MODE BIT

GET ACK

READ DATABYTE

INTREQ STILL LOW?

YES

SEND ACK

SEND NACK

SEND I2C STOP:

WHILE SCLK IS HIGH

RISING EDGE OF SCDIO

Figure 23. I2C® Read Flow Diagram

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