PCF8811USLASH2DASLASH1 datasheet(32/81 Pages) NXP

32 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

32 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

11.1.2 Bit transfer

One data bit is transferred during each clock pulse; see Figure 26. The data on the SDA

line must remain stable during the HIGH period of the clock pulse as changes in the data

line at this time will be interpreted as a control signal.

11.1.3 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P). The START and STOP conditions are shown in Figure 27.

11.1.4 Acknowledge

Each byte of eight bits is followed by an acknowledge bit; see Figure 28. The acknowledge

bit is a HIGH signal put on the bus by the transmitter during which time the master

generates an extra acknowledge-related clock pulse. A slave receiver which is addressed

must generate an acknowledge after the reception of each byte. A master receiver must

also generate an acknowledge after the reception of each byte that has been clocked out

of the slave transmitter. The device that acknowledges must pull-down the SDA line during

the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period

Fig 25. System conﬁguration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig 26. Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 27. Deﬁnition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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