PCF8811USLASH2DASLASH1 datasheet(65/81 Pages) NXP

65 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

65 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

[1]

All speciﬁed timings are based on 20 % and 80 % of VDD.

[2]

For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated.

[3]

A device must internally provide a data hold time to bridge the undeﬁned part between VIH and VIL of the falling edge of the SCLH

signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.

Table 35.

I2C-bus characteristics; Hs-mode

VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed[1]; see Figure 46.

Symbol

Parameter

Conditions

Cb = 100 pF (max)

Cb = 400 pF[2]

Unit

Min

Max

Min

Max

fSCLH

SCLH clock frequency

3.4

1.7

MHz

tSU;STA

set-up time for a repeated

START condition

160

tHD;STA

hold time (repeated) START

condition

160

tLOW

LOW period of the SCLH

clock

160

320

tHIGH

HIGH period of the SCLH

clock

120

tSU;DAT

data set-up time

tHD;DAT

data hold time

20[3]

150

trCL

rise time of SCLH signal

trCL1

rise time of SCLH signal after

a repeated START condition

and after an acknowledge bit

160

tfCL

fall time of SCLH signal

trDA

rise time of SDAH signal

160

tfDA

fall time of SDAH signal

160

tSU;STO

set-up time for STOP

condition

160

tSP

pulse width of spikes that

must be suppressed by the

input ﬁlter

SDAH and SCLH

capacitive load for each bus

line

SDAH and SCLH lines

[2]

100

400

SDAH + SDA line and

SCLH + SCL line

400

VnL

noise margin at the LOW level for each connected device

(including hysteresis)

0.1VDD1

-V

VnH

noise margin at the HIGH

level

for each connected device

(including hysteresis)

0.2VDD2

-V

PCF8811U/2DA/1 数据表(PDF) 65 Page - NXP Semiconductors

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