PCF8811USLASH2DASLASH1 datasheet(44/81 Pages) NXP

44 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

44 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

• Icons disabled (IC = 0)

• Address counter X[6:0] = 0 and Y[3:0] = 0

• Temperature control mode TC2 (TC[2:0] = 010)

• VLCD is equal to 0 V; the HV multiplier is switched off (PC[1:0] = 0)

• HV multiplier programming (VPR[7:0] = 0)

• 4

× voltage multiplier (S[2:0] = 100)

• Frame-rate frequency (FR[1:0] = 11)

• After power-on, RAM data is undeﬁned, the reset signal does not change the content

of the RAM

• All LCD outputs at VSS (display off)

• Full display selected (P[6:0] = multiplex rate 1:80 or 1:64)

• Initial display line set to line 0 (L[6:0] = 0)

• Initial row set to row 0 (C[6:0] = 0)

• Display is not mirrored (MX = 0; MY = 0)

• Internal oscillator is off

• Power-save mode is on

• Horizontal addressing enabled (V = 0)

• No data order swap (DOR = 0)

• No bottom row swap (BRS = 0)

• Internal oscillator enabled (EC = 0)

• No frame calibration running (OC = 0)

12.4 Power-save mode

In the Power-save mode the LCD driver has the following state:

• All LCD outputs at VSS (display off)

• Bias generator and VLCD generator switched off; external VLCD can be disconnected

• Oscillator off (external clock possible)

• RAM contents not cleared; RAM data can be written

• VLCD discharged to VSS in Power-down mode

There are two ways to put the chip into Power-save mode:

• The display must be off (DON = 0) and all the pixels on (DAL = 1)

• The Power-save mode command is activated

12.5 Display control

The bits DON, E and DAL select the display mode; see Table 13.

12.5.1 Bit MX

When MX = 0 the display RAM is written from left to right (X = 0 is on the left side and

X=Xmax is on the right side of the display).

PCF8811U/2DA/1 数据表(PDF) 44 Page - NXP Semiconductors

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