PCF8811USLASH2DASLASH1 datasheet(73/81 Pages) NXP

73 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

73 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

18.1.6 Example sequence for ﬁlling the shift register

An example of the sequence of commands and data is shown in Table 39. In this example

the shift register is ﬁlled with the following data: MMVOPCAL =

−4 (1 1100b), MMTC = 2

(010b) and the seal bit is logic 0.

It is assumed that the PCF8811 has just been reset. After transmitting the last bit the

PCF8811 can either exit or remain in the CALMM mode; see Table 39, Step 1. It should

be noted that while in CALMM mode the interface does not recognize commands in the

normal sense.

After this sequence has been applied it is possible to observe the impact of the data

shifted in. The described sequence is, however, not useful for OTP programming because

the number of bits with the value logic 1 is greater than that allowed for programming;

see Section 18.1.7. The shift register after this action is shown in Figure 53.

[1]

X = value without meaning.

[2]

The data for the bits is not in the correct shift register position until all bits have been sent.

18.1.7 Programming ﬂow

Programming is achieved whilst in CALMM mode and with the application of the

programming voltages. As mentioned previously, the data for programming the OTP cell is

contained in the corresponding shift register cell. The shift register cell must be loaded

Table 39.

Sequence for ﬁlling the shift register; example 1[1]

Step Pad

Command byte

Action

EXT

D/C

R/W/WR DB7

DB6

DB5

DB4 DB3 DB2 DB1 DB0

exit power-down

wait 5 ms for refresh to take effect

enter CALMM mode

shift in data; MMVOPCAL[4] is ﬁrst bit [2]

MMVOPCAL[3]

MMVOPCAL[2]

MMVOPCAL[1]

MMVOPCAL[0]

MMTC[2]

MMTC[1]

MMTC[0]

seal bit; exit CALMM mode

An alternative ending could be to stay in CALMM mode

seal bit; remain in CALMM mode

Fig 53. Shift register contents after example sequence; see Table 39

MSB

LSB

shifting

direction

mgw765

MMTC[2:0]

SEAL

BIT = 0

MSB

LSB

MMVOPCAL[4:0]

OTP SHIFT REGISTER

PCF8811U/2DA/1 数据表(PDF) 73 Page - NXP Semiconductors

PCF8811U/2DA/1 数据表(HTML) 73 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载