PCF8811USLASH2DASLASH1 datasheet(59/81 Pages) NXP

59 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

59 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

[2]

Valid for values of temperature, VPR and TC used at calibration.

[3]

During power-down all static currents are switched off.

[4]

Conditions are: VDD1 = 1.8 V, VDD2 = 2.7 V, VLCD = 8.05 V, voltage multiplier 4 × VDD2, inputs at VDD1 or VSS, interface inactive, internal

VLCD generation, VLCD output is loaded by 10 µA and Tamb = 25 °C.

[5]

Normal mode.

[6]

TC7 can only be used when VDD2 = VDD3 = 2.4 V or higher.

16. Dynamic characteristics

[1]

All speciﬁed timings are based on 20 % and 80 % of VDD.

[2]

RES can be LOW before VDD goes HIGH.

16.1 Parallel interface timing characteristics

Table 31.

Dynamic characteristics[1]

VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fext

external frequency

external clock

200

kHz

fframe

frame frequency

Tamb = 25 °C; VDD1 = 2.4 V

tVHRL

VDD to RES LOW

see Figure 47

[2] 0-

µs

tRW

RES LOW pulse width

see Figure 47

500

Table 32.

Parallel interface (6800 series) timing characteristics

VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed;

see Figure 39 and Figure 40.

Symbol

Parameter

Min

Max

Unit

tSU;DC

data/command set-up time

tHD;DC

data/command hold time

Tcyc(DS)

data strobe cycle time

1000

tDS(L)

data strobe LOW time

320

tDS(H)

data strobe HIGH time

300

tSU;RW

read/write set-up time

280

tHD;RW

read/write hold time

tSU;CE

chip enable set-up time

280

tHD;CE

chip enable hold time

tSU;DAT

data set-up time

tHD;DAT

data hold time

tDAT;ACC

data output access time

280

tDAT;OH

data output disable time

PCF8811U/2DA/1 数据表(PDF) 59 Page - NXP Semiconductors

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