TLK6002 datasheet(41/96 Pages) TI

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32"1's"

Pu1

PA4

PA0

D15

Idle

Start

Read

Code

PHY

Addr

Turn

Around

Data

REG

Addr

RA4

RA0

Preamble

MDC

MDIO

32 "1's"

PA[4:0]

D15

Idle

Start

Write

Code

PHY

Addr

Turn

Around

Data

REG

Addr

RA4

RA0

Preamble

MDC

MDIO

TLK6002

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SLLSE34 – MAY 2010

Table 2-10. MDIO Related Signals

SIGNAL

TYPE

DESCRIPTION

MDC

LVCMOS

Management Interface Clock. This clock is used to sample the MDIO signal.

1.5V/1.8V

Input VDDO3

MDIO

LVCMOS

Management Interface Data. Bidirectional data line for MDIO Port is sampled on the rising edge of MDC.

1.5V/1.8V

THIS SIGNAL MUST BE EXTERNALLY PULLED UP TO VDDO3. Consult IEEE802.3 Clause 22 for an appropriate

Input/OutputVDDO3

resistance value.

PRTAD[4:0]

LVCMOS

Port Address. Used to select the Port ID in Clause 22 MDIO mode.

1.5V/1.8V

PRTAD[4:1] selects a block of two sequential Clause 22 port addresses. Each channel is implemented as a different port

Input

address, and can be accessed by setting the appropriate port address field within the Clause 22 MDIO transaction.

VDDO2/ VDDO1/

VDDO1/ VDDO1/

PRTAD[0] is not used functionally, but is needed for device testability with other devices in the family of products.

VDDO1

Channel A responds to port address 0 within the block of two port addresses.

Channel B responds to port address 1 within the block of two port addresses.

It is possible for 16 TLK6002 devices to logically share an MDIO bus.

In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2

individual channels in TLK6002 are classified as 2 different ports. So for any PRTAD[4:1] value there will

be 2 ports per TLK6002.

TLK6002 will respond if the 4 MSB's of PHY address field on MDIO protocol (PA[4:1]) matches

PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel/port within TLK6002 to

respond to.

If PA[0] = 1b0, TLK6002 Channel A will respond.

If PA[0] = 1b1, TLK6002 Channel B will respond.

Write transactions which address an invalid register or device or a read only register will be ignored. Read

transactions which address an invalid register will return a 0.

MDIO Protocol Timing:

The Clause 22 timing required to read from the internal registers is shown in Figure 2-9. The Clause 22

timing required to write to the internal registers is shown in Figure 2-10.

(1)

Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK6002.

Figure 2-15. CL22 – Management Interface Read Timing

Figure 2-16. CL22 – Management Interface Write Timing

Description

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