 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TLK6002 数据表(PDF) 11 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TLK6002 数据表(HTML) 11 Page - Texas Instruments |
|
|
11 / 96 page  TLK6002 www.ti.com SLLSE34 – MAY 2010 Table 2-1. Pin Description – Signal Pins (continued) Terminal Direction Type Description Signal BGA Supply Channel B Receive Loss Of Signal (LOS) Indicator. LOSB=0, signal detected. LOSB=1, Loss of signal (6.10 enabled). Loss of signal detection is based on the input signal level. When RXBP/N has an input signal of ≤75 mVdfpp, LOSB will be asserted (if enabled). The input signal should be ≥ Output 150 mVdfpp for this function to operate reliably. LVCMOS LOSB V17 1.5V/1.8V Other functions can be observed on LOSB realtime, configured via MDIO. VDDO2 40 Ω During device reset (RESET_N asserted low) this pin is driven low. Driver During pin based power down (PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high), this pin is floating. It is highly recommended that LOSB be brought to easily accessible point on the application board (header), in the event that debug is required. Input Transceiver Power down. When this pin is held low (asserted), Channel B is placed in power down mode. When LVCMOS deasserted , Channel B operates normally. After deassertion, a software datapath reset should be issued through PD_TRXB_N U15 1.5V/1.8V the MDIO interface. VDDO2 Signals common to Channels A and B: Reference Clock Input Zero. This differential input is a clock signal used as a reference to either or both of the Input LVDS/ bidirectional SERDES macros. It can be routed internally to either SERDES macro using device pins B5 REFCLK_0_P/N LVPECL (REFCLK_A_SEL and REFCLK_B_SEL) or through software registers. This input signal must be AC coupled. See A5 DVDD Figure 1-3. TLK6002 Reference Clock / Output Clock Architecture for more detail. If unused, REFCLK_0_P/N should be pulled down to DGND through a shared 100 Ω resistor. Reference Clock Input One. This differential input is a clock signal used as a reference to either or both of the Input LVDS/ bidirectional SERDES macros. It can be routed internally to either SERDES macro using device pins C6 REFCLK_1_P/N LVPECL (REFCLK_A_SEL and REFCLK_B_SEL) or through software registers. This input signal must be AC coupled. See D6 DVDD Figure 1-3. TLK6002 Reference Clock / Output Clock Architecture for more detail. If unused, REFCLK_1_P/N should be pulled down to DGND through a shared 100 Ω resistor Input Reference Clock Select Channel A. This input, when low, selects REFCLK_0_P/N as the clock reference to LVCMOS Channel A SERDES macro. When high, REFCLK_1_P/N is selected as the clock reference to Channel A SERDES REFCLK_A_SEL R6 1.5V/1.8V macro. If software control is desired (register bit 0.1), this input signal should be tied low. See Figure 1-3. TLK6002 VDDO3 Reference Clock / Output Clock Architecture for more detail. Input Reference Clock Select Channel B. This input, when low, selects REFCLK_0_P/N as the clock reference to LVCMOS Channel B SERDES macro. When high, REFCLK_1_P/N is selected as the clock reference to Channel B SERDES REFCLK_B_SEL T2 1.5V/1.8V macro. If software control is desired (register bit 0.0), this input signal should be tied low. See Figure 1-3. TLK6002 VDDO3 Reference Clock/Output Clock Architecture for more detail. Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths of both channels. This signal is logically OR’d with an mdio register bit. Input PRBS 231-1 is selected by default, and can be changed in MDIO register 7.10:8. LVCMOS PRBS_EN R16 1.5V/1.8V Note that PRBS is not possible in eighth rate mode. VDDO2 The PRBS_EN pin should be routed to an uninstalled header so that it could be driven externally in the event that device debug is required. In application mode, it should be biased with a pull up or pull down resistor (or allow for an isolation mechanism from the on board driver), and not connected directly to a power or ground plane. Recovered Byte Clock. If ARS is not enabled, and CLK_OUT_SEL is low, an optionally divided version of Channel A recovered byte clock is output onto CLK_OUT_P/N. If ARS is not enabled, and CLK_OUT_SEL is high, an optionally divided version of Channel B recovered byte clock is output onto CLK_OUT_P/N. The recovered byte clock is synchronous to the incoming serial data rate for the selected channel. See Figure 1-3. TLK6002 Reference Clock/Output Clock Architecture for more detail. The recovered byte clock can be divided by one, two, four, or eight as selected in an mdio register. J6 Output CML CLK_OUT_P/N J7 DVDD If ARS is enabled, the CLK_OUT_P/N output is selected via Table 2-9. This CML output must be AC coupled. During device reset (RESET_N asserted low) this pin is driven differential zero. During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), these pins are floating. During register based power down (1.15 asserted high both channels), these pins are floating. Output Clock Selection. If ARS is not enabled and CLK_OUT_SEL is low, Channel A recovered byte clock is Input output onto CLK_OUT_P/N. If ARS is not enabled and CLK_OUT_SEL is high, Channel B recovered byte clock is LVCMOS CLK_OUT_SEL T15 output onto CLK_OUT_P/N. If software control is desired (register bit 0.6), this input signal should be tied low. See 1.5V/1.8V Figure 1-3. TLK6002 Reference Clock / Output Clock Architecture for more detail. If ARS is enabled, the function of VDDO2 CLK_OUT_SEL is shown in Table 2-9. Copyright © 2010, Texas Instruments Incorporated Description 11 Submit Documentation Feedback Product Folder Link(s): TLK6002 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
