TLK6002 datasheet(75/96 Pages) TI

75 / 96 page

OUTPUT

INPUT

PCB

50 W

VDDQ

GND

transmissionline

1kW

100

/200

/open( )

100

/200

/open( )

VREF*(VDDQ/2)

TLK6002

www.ti.com

SLLSE34 – MAY 2010

4.16 Power Sequencing Guidelines

The TLK6002 allows either the core or I/O power supply to be powered up for an indefinite period of time

while the other supply is not powered up, if all of the following conditions are met:

1. All maximum ratings and recommending operating conditions are followed

2. Bus contention while 1.5/1.8V power is applied (>0V) must be limited to 100 hours over the projected

lifetime of the device.

3. Junction temperature is less than 105°C during device operation. Note: Voltage stress up to the

absolute maximum voltage values for up to 100 hours of lifetime operation at a TJ of 105°C or lower

will minimally impact reliability.

The TLK6002 inputs are not failsafe (i.e. cannot be driven with the I/O power disabled). TLK6002 inputs

should not be driven high until their associated power supply is active.

4.17 HSTL Interface

The HSTL interface allows for either 1.5V or 1.8V operation. Source series (output) and parallel end

(input) resistance is dynamically updated to compensate for process, voltage, and temperature. RES*

device pins are referenced to accurately set the impedances.

The source series (HSTL output) impedance is dynamically calibrated to 50

Ω using an external 50 Ω

resistor.

There are three options on parallel end (HSTL input) termination:

1. No end termination. This yields the lowest power dissipation, at the cost of signal integrity

performance.

2. Half Strength Mode – 100

Ω Thevenin Equivalent – This mode is comprised of two 200 Ω resistors,

placed between the input signal and VDDQA/B, and the input signal and DGND. This selection yields a

blend between signal integrity performance and power dissipation.

3. Full Strength Mode – 50

Ω Thevenin Equivalent – This mode is comprised of two 100 Ω resistors,

placed between the input signal and VDDQA/B, and the input signal and DGND. This selection yields

the best signal integrity performance at the cost of highest power dissipation.

All three HSTL input modes can be selected through the MDIO interface on a per channel basis through

(6.2).

Figure 4-22 shows the schematic of the internal HSTL driver and internal HSTL receiver.

Figure 4-22. HSTL I/O Schematic

ELECTRICAL SPECIFICATIONS

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