TLK6002 datasheet(73/96 Pages) TI

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TXCLK_x

TDx

VIH(ac)

VDDQ/2

VIL(ac)

VIH(ac)

VDDQ/2

VIL(ac)

tPERIOD

tSETUPH tHOLDH

TXCLK_x

TDx

VIH(ac)

VDDQ/2

VIL(ac)

VIH(ac)

VDDQ/2

VIL(ac)

tPERIOD

tSETUPL tHOLDL

TLK6002

www.ti.com

SLLSE34 – MAY 2010

4.13 HSTL (SDR Timing Mode Only) Input Timing Requirements

PARAMETER

CONDITION

MIN

MAX

UNIT

tsetupH

TDx(1) setup prior to TXCLK_x(2) transition

480

Falling Edge Aligned (Rising Edge Sampled) Data,(3) See

high

Figure 4-18

tholdH

TDx hold after TXCLK_x transition high

480

tsetupL

TDx setup prior to TXCLK_x transition low

480

Rising Edge Aligned (Falling Edge Sampled) Data,(3) See

Figure 4-19

tholdL

TDx hold after TXCLK_x transition low

480

tduty

TXCLK_x Duty Cycle

Rising and Falling Edge Sampled Data

40%

60%

tperiod

TXCLK_x Period

Rising and Falling Edge Aligned Data

3.2

42.5

Tfreq

TXCLK_x Frequency

Rising and Falling Edge Aligned Data

23.5

312.

MHz

(1)

TDx refers to either channel A (TDA) or B (TDB).

(2)

TXCLK_x refers to either channel A (TXCLK_A) or channel B (TXCLK_B).

(3)

Input timing reference of (VDDQA/B)/2 with ±1 ns/V rise time on all input signals.

Figure 4-18. HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input

Timing Requirements

Figure 4-19. HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input

Timing Requirements

ELECTRICAL SPECIFICATIONS

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