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TLK6002 数据表(PDF) 17 Page - Texas Instruments |
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TLK6002 数据表(HTML) 17 Page - Texas Instruments |
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17 / 96 page  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A DGND RDA_12 VDDQA DGND REFCLK_0 _N DGND CGND XTALP CGND PRI_REF2P CGND CGND RC1 RC3 DGND RDB_7 RDB_13 DGND B RDA_17 VDDQA RDA_18 DGND REFCLK_0 _P DGND VDD_XTAL XTALN VDD_PRI_I N2 PRI_REF2N VDD_PLL2 LF2B AMUX RC2 RDB_6 RDB_12 VDDQB RDB_17 C RDA_9 RDA_16 RDA_11 VDDQA DGND REFCLK_1 _P LF1B VDD_SREF VDD_SEC_ IN2 CGND VDD_CP2_ PFD2 LF2A CGND CMSEL VDDQB RDB_11 RDB_16 RDB_9 D RDA_19 DGND RDA_10 RDA_7 DGND REFCLK_1 _N LF1A CGND SYNTHREF CGND CGND CGND RFOUTN CS_N RDB_5 RDB_10 DGND RDB_19 E VDDQA RDA_15 DGND RDA_6 RDA_2 VDD_CP1_ PFD1 VDD_PLL1 CGND CGND CGND CGND VDD_VCO RFOUTP SDI RDB_4 DGND RDB_18 VDDQB F RXCLK_A RDA_14 RDA_13 RDA_8 VDDQA VDD_PRI_I N1 FBINN CGND CGND CGND CGND VDD_RF_P S VDD18 VDDQB RDB_8 RDB_15 RDB_14 RXCLK_B G DGND VDDQA RDA_4 RDA_5 RDA_0 VDD_FBIN FBINP CGND CGND CGND CGND CGND VDD_DIG_ IO RDB_0 RDB_1 RDB_3 VDDQB DGND H TDA_19 TDA_17 DGND RDA_3 RDA_1 VDD_SEC_ IN1 CGND Y3N Y3P Y0N Y0P CGND SCL DGND RDB_2 DGND TDB_18 TDB_16 J TDA_14 TDA_15 TDA_18 VDDQA DGND CLK_OUT_ P CLK_OUT_ N VDD_Y4 VDD_Y3 VDD_Y2 VDD_Y1 VDD_Y0 PDN RESRB VDDQB TDB_17 TDB_19 TDB_5 K VDDQA DGND TDA_8 TDA_16 TDA_13 DGND RESETN RESRA VPP GPI1 PRTAD1 PRTAD2 SDO DGND TDB_15 TDB_14 DGND VDDQB L VREFTA DGND TDA_12 VDDQA TDA_11 DVDD VDDQA VDDQA DVDD VDDO1 PRTAD0 VDDQB DVDD TDB_13 VDDQB TDB_12 VDDQB VREFTB M RESTA TDA_5 TDA_10 TDA_9 TDA_7 VDDQA DGND PRTAD3 DGND DVDD DGND DVDD VDDQB TDB_11 TDB_9 TDB_10 TDB_4 RESTB N VDDQA DGND TDA_6 DGND TDA_2 DVDD DGND DGND VDD33 DGND DGND DGND DVDD TDB_7 DGND TDB_6 DGND VDDQB P TXCLK_A TDA_4 VDDQA TDA_3 TDA_0 VDDQA DGND DGND DGND DGND DGND DGND VDDQB TDB_1 TDB_2 VDDQB TDB_8 TDB_0 R DGND TDA_1 TMS GPI0 DGND REFCLK_A _SEL VDDO3 DVDD AGND DVDD AGND DVDD VDDO2 TDO TDI PRBS_EN TDB_3 DGND T MDC REFCLK_B _SEL TRST_N RATE_A1 DVDD PD_TRXA_ N VDDRA VDDD AVDD AVDD VDDD VDDRB AVDD AGND CLK_OUT_ SEL TCK TESTEN TXCLK_B U DGND MDIO RATE_A0 LOSA AMUXA AVDD AGND RXAN RXAP AGND AVDD TXBP TXBN AVDD PD_TRXB_ N RATE_B2 RATE_B1 RATE_B0 V RESET_N RATE_A2 PRBSA_PA SS CODEA_EN AGND TXAN TXAP VDDT AGND RXBP RXBN VDDT AGND AMUXB PRTAD4 CODEB_EN LOSB PRBSB_PA SS TLK6002 www.ti.com SLLSE34 – MAY 2010 2.2 Device Pinout Diagram Table 2-3. Device Pinout Diagram – (Top View) 2.3 CPRI/OBSAI Specific Operation Modes The TLK6002 contains an internal low-jitter high quality oscillator that is used as a frequency multiplier for the serdes and other internal circuits of the device. The rate pins (and mdio registers) as well as the SERDES PLL multiplier are used to program the line rate and the REFCLK frequency for various applications. See Appendix B for more details on SERDES reference clock, rate, and multiplier selection (rates beyond the CPRI/OBSAI specific rates). The TLK6002 is optimized for operation at a serial data rate of 470 Mbit/s through 6.25 Gbit/s. The external differential reference clock has a large operating frequency range allowing support for many different applications. The reference clock frequency must be within ±200 PPM of the incoming serial data rate (±100 PPM of nominal data rate), and have less than 40ps of jitter. Table 2-4 and Table 2-5 show a summary of frequency ranges used for the CPRI and OBSAI applications. The transmit parallel input clock must be frequency locked (0 ppm) to the supplied/selected reference clock (REFCLK_0/1_P/N) frequency. Table 2-4. CPRI Line Rate Selection(1) LINE RATE SERDES PLL RATE SELECT (PINS OR TXCLK_A/B REFCLKP/N (Mbps) MULTIPLIER VALUE REGISTER VALUE) (MHz) (MHz) 6144.00 20/25 Full 307.2 153.60/122.88 4915.20 16/20 Full 245.76 153.60/122.88 3072.00 20/25 Half 153.6 153.60/122.88 2457.60 16/20 Half 122.88 153.60/122.88 1228.80 16/20 Quarter 61.44 153.60/122.88 614.40 16/20 Eighth 30.72 153.60/122.88 (1) In DDR mode TX_CLK frequencies will be half the values in the table above. The table above indicate two possible REFCLK frequencies, 153.60MHz and 122.88MHz which can be used based on the application preference. The Serdes PLL Multiplier (MPY) has been given for each REFCLK frequency respectively. Note that Channel A and B are independent, and their application rates and references clocks are separate. Copyright © 2010, Texas Instruments Incorporated Description 17 Submit Documentation Feedback Product Folder Link(s): TLK6002 |
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