TLK6002 datasheet(8/96 Pages) TI

8 / 96 page

TLK6002

SLLSE34 – MAY 2010

www.ti.com

Table 2-1. Pin Description – Signal Pins (continued)

Terminal

Direction

Type

Description

Signal

BGA

Supply

Channel A Rate select pins. These pins put channel A into one of the four supported (full/half/quarter/eighth)

channel operation rates, enable software control, or enable Auto Rate Sense (ARS):

000 – Full Rate mode

001 – Half Rate mode

010 – Quarter rate mode

011 – Eighth rate mode

100 – Software Selectable Rate (Recommended default board configuration)

101 – Channel A Auto Rate Sense (ARS) Function Enabled

Channel A SERDES settings are determined by Channel A ARS machine.

CLK_OUT_P/N selected by CLK_OUT_SEL

See Table 2-9 for additional details on CLK_OUT_P/N.

110 – Channel A Auto Rate Sense (ARS) Function Enabled

Channel A SERDES settings are determined by Channel A ARS machine.

CLK_OUT_P/N is not selected by CLK_OUT_SEL

Input

Channel B may not be simultaneously configured with RATE_B=110

LVCMOS

With respect to CLK_OUT_P/N, this setting has the highest priority.

RATE_A[2:0]

1.5V/1.8V

See Table 2-9 for additional details on CLK_OUT_P/N.

VDDO3

111 – Channel A Auto Rate Sense (ARS) Function Enabled – Slave Mode

If Channel B ARS is enabled (RATE_B=101 or 110 only):

Channel A SERDES settings are determined by Channel B ARS machine.

CLK_OUT_P/N is not selected by CLK_OUT_SEL

See Table 2-9 for additional details on CLK_OUT_P/N.

If Channel B ARS is not enabled (RATE_B=000/001/010/011/111):

Channel A SERDES settings are determined by Channel A MDIO registers.

CLK_OUT_P/N selected by CLK_OUT_SEL

See Table 2-9 for additional details on CLK_OUT_P/N.

Channel A and B should not be in slave mode simultaneously. Both directions of Channel A are controlled by these

input signals.

The RATE_A[2] pin should be routed to an uninstalled header so that it could be driven externally in the event that

device debug is required. In application mode, it should be biased with a pull up or pull down resistor, and not

connected directly to a power or ground plane.

Receive Output Channel A Clock. RXCLK_A is synchronous to RDA_[19:0], and may be used externally to

sample Channel A output parallel data.

Output

In SDR mode, this signal is equal in frequency to serial bit rate / 20.

HSTL

RXCLK_A

In DDR mode, this signal is equal in frequency to serial bit rate / 40.

1.5V/1.8V

VDDQA

During device reset (RESET_N asserted low) this pin is driven low.

During pin based power down (PD_TRXA_N asserted low), this pin is floating.

During register based power down (1.15 asserted high), these pins are floating.

Receive PRBS Channel A Error Free (Pass) Indicator

When PRBS test is enabled (PRBS_EN=1):

PRBSA_PASS=1 indicates that PRBS pattern reception is error free.

Output

PRBSA_PASS=0 indicates that a PRBS error is detected.

LVCMOS

During device reset (RESET_N asserted low) this pin is driven low.

PRBSA_PASS

1.5V/1.8V

During pin based power down (PD_TRXA_N asserted low), this pin is floating.

VDDO3 40

During register based power down (1.15 asserted high), this pin is floating.

Driver

It is highly recommended that PRBSA_PASS be brought to easily accessible point on the application board

(header), in the event that debug is required.

Encoder/Decoder Channel A Enable: When this pin is asserted high, the internal 8b/10b encoder/decoder is

Input

enabled. This signal is OR’d with MDIO register bits, and should be pulled low through a resistor if software control

LVCMOS

CODEA_EN

is desired. This pin should be routed to an uninstalled header so that it could be driven externally in the event that

1.5V/1.8V

device debug is required. In application mode, it should be biased with a pull up or pull down resistor, and not

VDDO3

connected directly to a power or ground plane.

Channel A Receive Loss Of Signal (LOS) Indicator.

LOSA = 0, signal detected.

LOSA = 1, Loss of signal (6.10 enabled).

Loss of signal detection is based on the input signal level.

Output

When RXAP/N has an input signal of

≤75 mVdfpp, LOSA will be asserted (if enabled). The input signal should be ≥

LVCMOS

150 mVdfpp for this function to operate reliably.

LOSA

1.5V/1.8V

Other functions can be observed on LOSA realtime, configured via MDIO.

VDDO3 40

Driver

During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PD_TRXA_N

asserted low), this pin is floating. During register based power down (1.15 asserted high), this pin is floating.

It is highly recommended that LOSA be brought to easily accessible point on the application board (header), in the

event that debug is required.

Description

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