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XIO2001IPNP 数据表(PDF) 49 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 49 Page - Texas Instruments |
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49 / 131 page  XIO2001 www.ti.com SCPS212D – MAY 2009 – REVISED JANUARY 2010 4.14 Secondary Latency Timer Register This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles. PCI register offset: 1Bh Register type: Read/Write Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 4.15 I/O Base Register This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream. See Table 4-6 for a complete description of the register contents. PCI register offset: 1Ch Register type: Read-only, Read/Write Default value: 01h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 Table 4-6. I/O Base Register Description BIT FIELD NAME ACCESS DESCRIPTION I/O base. Defines the bottom address of the I/O address range that determines when to forward I/O transactions from one interface to the other. These bits correspond to address bits [15:12] in the I/O 7:4 IOBASE RW address. The lower 12 bits are assumed to be 000h. The 16 bits corresponding to address bits [31:16] of the I/O address are defined in the I/O base upper 16 bits register (offset 30h, see Section 4.24). 3:0 IOTYPE R I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing. 4.16 I/O Limit Register This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream. See Table 4-7 for a complete description of the register contents. PCI register offset: 1Dh Register type: Read-only, Read/Write Default value: 01h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 Table 4-7. I/O Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION I/O limit. Defines the top address of the I/O address range that determines when to forward I/O transactions from one interface to the other. These bits correspond to address bits [15:12] in the I/O 7:4 IOLIMIT RW address. The lower 12 bits are assumed to be FFFh. The 16 bits corresponding to address bits [31:16] of the I/O address are defined in the I/O limit upper 16 bits register (offset 32h, see Section 4.25). 3:0 IOTYPE R I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing. Copyright © 2009–2010, Texas Instruments Incorporated Classic PCI Configuration Space 49 Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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