XIO2001IPNP datasheet(24/131 Pages) TI

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and

DD_15

DDA_15

and

DD_33

DDA_33

PCIR

REFCLK

PERST

XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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3.1.2

Power-Down Sequence

1. Assert PERST to the device.

2. Remove the reference clock.

3. Remove PCIR clamp voltage.

4. Remove 3.3-V and 1.5-V voltages.

See the power-down sequencing diagram in Figure 3-3. If the VDD_33_AUX terminal is to remain powered

after a system shutdown, then the bridge power-down sequence is exactly the same as shown in

Figure 3-3.

Figure 3-3. Power-Down Sequence

3.2

Bridge Reset Features

There are five bridge reset options that include internally-generated power-on reset, resets generated by

asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot

reset or setting a configuration register bit. Table 3-1 identifies these reset sources and describes how the

bridge responds to each reset.

Table 3-1. XIO2001 Reset Options

RESET

XIO2001 FEATURE

RESET RESPONSE

OPTION

Bridge

During a power-on cycle, the bridge asserts an internal reset When the internal power-on reset is asserted, all control

internally-

and monitors the VDD_15_COMB terminal. When this terminal

registers, state machines, sticky register bits, and power

generated

reaches 90% of the nominal input voltage specification,

management state machines are initialized to their default

power-on reset

power is considered stable. After stable power, the bridge

state.

monitors the PCI Express reference clock (REFCLK) and

In addition, the XIO2001 asserts the internal PCI bus reset.

waits 10 ms after active clocks are detected. Then, internal

power-on reset is deasserted.

Global reset

When GRST is asserted low, an internal power-on reset

When GRST is asserted low, all control registers, state

input

occurs. This reset is asynchronous and functions during

machines, sticky register bits, and power management

GRST

both normal power states and VAUX power states.

state machines are initialized to their default state. In

addition, the bridge asserts PCI bus reset (PRST). When

the rising edge of GRST occurs, the bridge samples the

state of all static control inputs and latches the information

internally. If an external serial EEPROM is detected, then a

download cycle is initiated. Also, the process to configure

and initialize the PCI Express link is started. The bridge

starts link training within 80 ms after GRST is deasserted.

Feature/Protocol Descriptions

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