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XIO2001IPNP 数据表(PDF) 85 Page - Texas Instruments

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部件名 XIO2001IPNP
功能描述  PCI Express??to PCI Bus Translation Bridge
PDF  131 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

XIO2001IPNP 数据表(HTML) 85 Page - Texas Instruments

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XIO2001
www.ti.com
SCPS212D – MAY 2009 – REVISED JANUARY 2010
Table 4-46. Serial IRQ Mode Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:4
RSVD
R
Reserved. Returns 0h when read.
Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.
00 = 4 clocks (default)
3:2(1)
START_WIDTH
RW
01 = 6 clocks
10 = 8 clocks
11 = Reserved
Poll mode. This bit selects between continuous and quiet mode.
1(1)
POLLMODE
RW
0 = Continuous mode (default)
1 = Quiet mode
RW Drive mode. This bit selects the behavior of the serial IRQ controller during the
recovery cycle.
0(1)
DRIVEMODE
RW
0 = Drive high (default)
1 = 3-state
(1)
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.73 Serial IRQ Edge Control Register
This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. See Table 4-47
for a complete description of the register contents.
PCI register offset:
E2h
Register type:
Read/Write
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-47. Serial IRQ Edge Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
IRQ 15 edge mode
15(1)
IRQ15_MODE
RW
0 = Edge mode (default)
1 = Level mode
IRQ 14 edge mode
14(1)
IRQ14_MODE
RW
0 = Edge mode (default)
1 = Level mode
IRQ 13 edge mode
13(1)
IRQ13_MODE
RW
0 = Edge mode (default)
1 = Level mode
IRQ 12 edge mode
12(1)
IRQ12_MODE
RW
0 = Edge mode (default)
1 = Level mode
(1)
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Copyright © 2009–2010, Texas Instruments Incorporated
Classic PCI Configuration Space
85
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Product Folder Link(s): XIO2001



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