XIO2001IPNP datasheet(22/131 Pages) TI

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PCI Express

Transmitter

PCI Express

Receiver

PCI Bus Interface

Configuration and

Memory Register

GPIO

Serial

EEPROM

Serial

IRQ

Reset

Controller

Clock

Generator

Power

Mgmt

XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

www.ti.com

Feature/Protocol Descriptions

This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified

block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the

PCI Express interface and the PCI bus interface is located at the bottom of the diagram.

Figure 3-1. XIO2001 Block Diagram

3.1

Power-Up/-Down Sequencing

The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down

sequences describe how power is applied to these terminals.

In addition, the bridge has three resets: PERST, GRST and an internal power-on reset. These resets are

fully described in Section 3.2. The following power-up and power-down sequences describe how PERST

is applied to the bridge.

The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down

sequence and is included in the following power-up and power-down descriptions.

Feature/Protocol Descriptions

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