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XIO2001IPNP 数据表(PDF) 88 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 88 Page - Texas Instruments |
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88 / 131 page  XIO2001 SCPS212D – MAY 2009 – REVISED JANUARY 2010 www.ti.com Table 4-48. Serial IRQ Status Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION IRQ 6 asserted. This bit indicates that the IRQ6 has been asserted. 6(1) IRQ6 RCU 0 = Deasserted 1 = Asserted IRQ 5 asserted. This bit indicates that the IRQ5 has been asserted. 5(1) IRQ5 RCU 0 = Deasserted 1 = Asserted IRQ 4 asserted. This bit indicates that the IRQ4 has been asserted. 4(1) IRQ4 RCU 0 = Deasserted 1 = Asserted IRQ 3 asserted. This bit indicates that the IRQ3 has been asserted. 3(1) IRQ3 RCU 0 = Deasserted 1 = Asserted IRQ 2 asserted. This bit indicates that the IRQ2 has been asserted. 2(1) IRQ2 RCU 0 = Deasserted 1 = Asserted IRQ 1 asserted. This bit indicates that the IRQ1 has been asserted. 1(1) IRQ1 RCU 0 = Deasserted 1 = Asserted IRQ 0 asserted. This bit indicates that the IRQ0 has been asserted. 0(1) IRQ0 RCU 0 = Deasserted 1 = Asserted 4.75 Pre-Fetch Agent Request Limits Register This register is used to set the Pre-Fetch Agent's limits on retrieving data using upstream reads. See Table 4-49 for a complete description of the register contents. PCI register offset: E8h Register type: Read/Clear Default value: 0443h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 88 Classic PCI Configuration Space Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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