XIO2001IPNP datasheet(64/131 Pages) TI

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XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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4.49 Device Capabilities Register

The device capabilities register indicates the device specific capabilities of the bridge. See Table 4-25 for

a complete description of the register contents.

PCI register offset:

74h

Read-only

Default value:

0000 8D82

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 4-25. Device Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:28

RSVD

Reserved. Returns 0h when read.

27:26

CSPLS

Captured slot power limit scale. The value in this field is programmed by the host by issuing a

Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8

are written to this field. The value in this field specifies the scale used for the slot power limit.

00 = 1.0x

01 = 0.1x

10 = 0.01x

11 = 0.001x

25:18

CSPLV

Captured slot power limit value. The value in this field is programmed by the host by issuing a

Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0

are written to this field. The value in this field in combination with the slot power limit scale value

(bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is calculated

by multiplying the value in this field by the value in the slot power limit scale field.

17:16

RSVD

Reserved. Return 00b when read.

RBER

Role based error reporting. This bit is hardwired to 1 indicating that this bridge supports Role

Based Error Reporting.

PIP

Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not

implemented.

AIP

Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is not

implemented.

ABP

Attention button present. This bit is hardwired to 0b indicating that an attention button is not

implemented.

11:9

EP_L1_LAT

Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a

transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY

field (bits 15:13) in the general control register (offset D4h, see Section 4.65). The default value

for this field is 110b which indicates a range from 32ms to 64ms. This field cannot be

programmed to be less than the latency for the PHY to exit the L1 state.

8:6

EP_L0S_LAT

Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a

transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY

field (bits 18:16) in the general control register (offset D4h, see Section 4.65). The default value

for this field is 110b which indicates a range from 2ms to 4ms. This field cannot be programmed

to be less than the latency for the PHY to exit the L0s state.

ETFS

Extended tag field supported. This field indicates the size of the tag field not supported.

4:3

PFS

Phantom functions supported. This field is read-only 00b indicating that function numbers are

not used for phantom functions.

2:0

MPSS

Maximum payload size supported. This field indicates the maximum payload size that the

device can support for TLPs. This field is encoded as 010b indicating the maximum payload

size for a TLP is 512 bytes.

Classic PCI Configuration Space

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