XIO2001IPNP datasheet(2/131 Pages) TI

2 / 131 page

XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

www.ti.com

Contents

Introduction

........................................................................................................................ 9

1.1

Features

...................................................................................................................... 9

Overview

.......................................................................................................................... 10

2.1

Description

................................................................................................................. 10

2.2

Related Documents

....................................................................................................... 10

2.3

Documents Conventions

.................................................................................................. 11

2.4

Document History

......................................................................................................... 11

2.5

Terminal Assignments

.................................................................................................... 11

2.6

Terminal Descriptions

..................................................................................................... 15

Feature/Protocol Descriptions

............................................................................................. 22

3.1

Power-Up/-Down Sequencing

........................................................................................... 22

3.1.1

Power-Up Sequence

........................................................................................... 23

3.1.2

Power-Down Sequence

........................................................................................ 24

3.2

Bridge Reset Features

.................................................................................................... 24

3.3

PCI Express Interface

..................................................................................................... 25

3.3.1

External Reference Clock

..................................................................................... 25

3.3.2

Beacon

........................................................................................................... 26

3.3.3

Wake

............................................................................................................. 26

3.3.4

Initial Flow Control Credits

.................................................................................... 26

3.3.5

PCI Express Message Transactions

......................................................................... 26

3.4

PCI Bus Interface

.......................................................................................................... 27

3.4.1

I/O Characteristics

.............................................................................................. 27

3.4.2

Clamping Voltage

............................................................................................... 27

3.4.3

PCI Bus Clock Run

............................................................................................. 28

3.4.4

PCI Bus External Arbiter

....................................................................................... 28

3.4.5

MSI Messages Generated from the Serial IRQ Interface

................................................. 28

3.4.6

PCI Bus Clocks

................................................................................................. 29

3.5

PCI Port Arbitration

........................................................................................................ 30

3.5.1

Classic PCI Arbiter

............................................................................................. 30

3.6

Configuration Register Translation

...................................................................................... 30

3.7

PCI Interrupt Conversion to PCI Express Messages

................................................................. 32

3.8

PME Conversion to PCI Express Messages

........................................................................... 32

3.9

PCI Express to PCI Bus Lock Conversion

............................................................................. 33

3.10

Two-Wire Serial-Bus Interface

........................................................................................... 34

3.10.1

Serial-Bus Interface Implementation

......................................................................... 34

3.10.2

Serial-Bus Interface Protocol

.................................................................................. 35

3.10.3

Serial-Bus EEPROM Application

............................................................................. 37

3.10.4

Accessing Serial-Bus Devices Through Software

.......................................................... 39

3.11

Advanced Error Reporting Registers

................................................................................... 39

3.12

Data Error Forwarding Capability

....................................................................................... 39

3.13

General-Purpose I/O Interface

........................................................................................... 40

3.14

Set Slot Power Limit Functionality

....................................................................................... 40

3.15

PCI Express and PCI Bus Power Management

....................................................................... 40

3.16

Auto Pre-Fetch Agent

..................................................................................................... 41

Classic PCI Configuration Space

......................................................................................... 42

Contents

XIO2001IPNP 数据表(PDF) 2 Page - Texas Instruments

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