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MPC8572ECLPXAVND 数据表(PDF) 134 Page - Freescale Semiconductor, Inc |
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MPC8572ECLPXAVND 数据表(HTML) 134 Page - Freescale Semiconductor, Inc |
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134 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 134 Freescale Semiconductor System Design Information • SD2_TX[3:0] • SD2_TX[3:0] • Reserved pins: AF26, AF27 The following pins must be connected to XGND_SRDS2: • SD2_RX[3:0] • SD2_RX[3:0] • SD2_REF_CLK • SD2_REF_CLK The POR configuration pin cfg_srds_sgmii_en on UART_RTS[1] can be used to power down SerDes 2 block for power saving. Note that both SVDD_SRDS2 and XVDD_SRDS2 must remain powered. 21.10.4 SerDes 2 Interface (SGMII) Partly Unused If only part of the high speed SerDes 2 interface (SGMII) pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float): • SD2_TX[3:0] • SD2_TX[3:0] • Reserved pins: AF26, AF27 The following pins must be connected to XGND_SRDS2: • SD2_RX[3:0] • SD2_RX[3:0] |
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