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MPC8572ECLPXAVND 数据表(PDF) 132 Page - Freescale Semiconductor, Inc

部件名 MPC8572ECLPXAVND
功能描述  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
PDF  140 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8572ECLPXAVND 数据表(HTML) 132 Page - Freescale Semiconductor, Inc

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
132
Freescale Semiconductor
System Design Information
Figure 66. JTAG Interface Connection
HRESET
From Target
Board Sources
COP_HRESET
13
COP_SRESET
SRESET
NC
11
COP_VDD_SENSE2
6
15
10
Ω
10 k
Ω
10 k
Ω
COP_CHKSTP_IN
CKSTP_IN0
8
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
9
1
3
4
COP_TRST
7
16
2
10
12
(if any)
14 3
Notes:
10 k
Ω
TRST1
10 k
Ω
10 k
Ω
10 k
Ω
CKSTP_OUT0
COP_CHKSTP_OUT
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pinout
1
2
NC
SRESET
2. Populate this with a 10
Ω resistor for short-circuit/current-limiting protection.
NC
OVDD
10 k
Ω
HRESET1
to fully control the processor as shown here.
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
signal integrity.
TCK
4
5
5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to position B.
10 k
Ω
6
6. Asserting SRESET causes a machine check interrupt to the e500 cores.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
A
B
5
10 k
Ω
CKSTP_OUT1
CKSTP_IN1



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