MPC8572ECLPXAVND datasheet(129/140 Pages) FREESCALE

129 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

129

System Design Information

Table 84 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,

nominal OVDD, 105°C.

21.8

Configuration Pin Muxing

The MPC8572E provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped

with an on-chip gated resistor of approximately 20 k

Ω. This value should permit the 4.7-kΩ resistor to pull

the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and

for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input

receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with

minimal signal quality or delay disruption. The default value for all configuration bits treated this way has

been encoded such that a high voltage level puts the device into the default state and external resistors are

needed only when non-default settings are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value

of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus

configured.

The platform PLL ratio, DDR complex PLL and e500 PLL ratio configuration pins are not equipped with

these default pull-up devices.

21.9

JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 66. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion gives

unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE Std 1149.1 specification, but it is provided on all processors built on Power Architecture technology.

The device requires TRST to be asserted during power-on reset flow to ensure that the JTAG boundary

logic does not interfere with normal chip operation. While the TAP controller can be forced to the reset

Table 84. Impedance Characteristics

Impedance

Local Bus, Ethernet, DUART,

Control, Configuration, Power

Management

DDR DRAM

Symbol

Unit

45 Target

18 Target (full strength mode)

36 Target (half strength mode)

45 Target

18 Target (full strength mode)

36 Target (half strength mode)

Note: Nominal supply voltages. See Table 1, Tj = 105°C.

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