MPC8572ECLPXAVND datasheet(127/140 Pages) FREESCALE

127 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

127

System Design Information

of the device. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD,

OVDD, GVDD, and LVDD, and GND power planes in the PCB, utilizing short traces to minimize

inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others

may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

Additionally, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the

smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating

to ensure the quick response time necessary. They should also be connected to the power and ground

planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON).

21.4

SerDes Block Power Supply Decoupling Recommendations

The SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SVDD_SRDSn and

XVDD_SRDSn) to ensure low jitter on transmit and reliable recovery of data in the receiver. An

appropriate decoupling scheme is outlined below.

Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections

from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

•

First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible

to the supply balls of the device. Where the board has blind vias, these capacitors should be placed

directly below the chip supply and ground connections. Where the board does not have blind vias,

these capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SVDD_SRDSn

and XVDD_SRDSn) to the board ground plane on each side of the device. This should be done for

all SerDes supplies.

•

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low

equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT

tantalum chip capacitor. This should be done for all SerDes supplies.

21.5

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. All unused active low inputs should be tied to VDD,TVDD, BVDD, OVDD, GVDD, and LVDD, as

required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnected. Power and ground connections must be made to all external VDD,TVDD, BVDD,

OVDD, GVDD, and LVDD, and GND pins of the device.

21.6

Pull-Up and Pull-Down Resistor Requirements

The MPC8572E requires weak pull-up resistors (2–10 k

Ω is recommended) on open drain type pins

including I2C pins and MPIC interrupt pins.

MPC8572ECLPXAVND 数据表(PDF) 127 Page - Freescale Semiconductor, Inc

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