MPC8572ECLPXAVND datasheet(128/140 Pages) FREESCALE

128 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

128

Freescale Semiconductor

System Design Information

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 66. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion gives

unpredictable results.

The following pins must NOT be pulled down during power-on reset: DMA_DACK[0:1], EC5_MDC,

HRESET_REQ, TRIG_OUT/READY_P0/QUIESCE, MSRCID[2:4], MDVAL, and ASLEEP. The

TEST_SEL pin must be set to a proper state during POR configuration. For more details, refer to the pinlist

table of the individual device.

21.7

Output Buffer DC Impedance

The MPC8572E drivers are characterized over process, voltage, and temperature. For all buses, the driver

is a push-pull single-ended driver type (open drain for I2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD

or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 64). The

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals

OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in value. Then, Z0 = (RP + RN)/2.

Figure 64. Driver Impedance Measurement

OVDD

OGND

Pad

Data

SW1

SW2

MPC8572ECLPXAVND 数据表(PDF) 128 Page - Freescale Semiconductor, Inc