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MSP430F2012IN 数据表(PDF) 49 Page - Texas Instruments |
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MSP430F2012IN 数据表(HTML) 49 Page - Texas Instruments |
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49 / 91 page ![]() Bus Keeper EN Direction 0: Input 1: Output P1SEL.x 1 0 P1DIR.x P1IN.x P1IRQ.x D EN Module X IN 1 0 Module X OUT P1OUT.x Interrupt Edge Select Q EN Set P1SEL.x P1IES.x P1IFG.x P1IE.x P1.0/TACLK/ACLK/CA0 P1.1/TA0/CA1 P1.2/TA1/CA2 P1.3/CAOUT/CA3 1 0 DVSS DVCC P1REN.x CAPD.x Pad Logic From Comparator_A+ To Comparator_A+ 1 MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491G – AUGUST 2005 – REVISED APRIL 2011 APPLICATION INFORMATION, MSP430F20X1 Port P1 (P1.0 to P1.3) Pin Schematics, MSP430F20x1 Table 16. Control Signal " From Comparator_A+" SIGNAL "From Comparator_A+" = 1(1) PIN NAME FUNCTION P2CA4 P2CA0 P2CA3 P2CA2 P2CA1 P1.0/TACLK/ACLK/CA0 CA0 0 1 N/A N/A N/A P1.1/TA0/CA1 CA1 1 0 0 0 1 OR P1.2/TA1/CA2 CA2 1 1 0 1 0 P1.3/CAOUT/CA3 CA3 N/A N/A 0 1 1 (1) N/A = Not available or not applicable Copyright © 2005–2011, Texas Instruments Incorporated 49 |
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