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MSP430F2012IN 数据表(PDF) 15 Page - Texas Instruments |
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MSP430F2012IN 数据表(HTML) 15 Page - Texas Instruments |
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15 / 91 page  MSP430F20x3 MSP430F20x2 MSP430F20x1 www.ti.com SLAS491G – AUGUST 2005 – REVISED APRIL 2011 Memory Organization Table 10. Memory Organization MSP430F200x MSP430F201x Memory Size 1KB Flash 2KB Flash Main: interrupt vector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main: code memory Flash 0FFFFh-0FC00h 0FFFFh-0F800h Size 256 Byte 256 Byte Information memory Flash 010FFh - 01000h 010FFh - 01000h 128 Byte 128 Byte RAM Size 027Fh - 0200h 027Fh - 0200h 16-bit 01FFh - 0100h 01FFh - 0100h Peripherals 8-bit 0FFh - 010h 0FFh - 010h 8-bit SFR 0Fh - 00h 0Fh - 00h Flash Memory The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. • Segments 0 to n may be erased in one step, or each segment may be individually erased. • Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. • Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. Copyright © 2005–2011, Texas Instruments Incorporated 15 |
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