MSP430F2012IN datasheet(58/91 Pages) TI

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Bus

Keeper

Direction

0: Input

1: Output

P1SEL.3

P1DIR.3

P1IN.3

P1IRQ.3

Module X IN

Module X OUT

P1OUT.3

Interrupt

Edge

Select

Set

P1SEL.3

P1IES.3

P1IFG.3

P1IE.3

P1.3/ADC10CLK/

A3/VREF−/VeREF−

DVSS

DVCC

P1REN.3

ADC10AE.3

To ADC 10 V

Pad Logic

INCHx = 3

R−

SREF2

VSS

MSP430F20x3

MSP430F20x2

MSP430F20x1

SLAS491G

– AUGUST 2005 – REVISED APRIL 2011

www.ti.com

Port P1 (P1.3) Pin Schematics, MSP430F20x2

Table 24. Port P1 (P1.3) Pin Functions, MSP430F20x2

CONTROL BITS / SIGNALS(1)(2)

PIN NAME (P1.x)

FUNCTION

P1DIR.x

P1SEL.x

ADC10AE.x

INCHx

P1.3(3) input/output

0/1

N/A

P1.3/ADC10CLK/A3/

ADC10CLK

N/A

VREF-/VeREF-

A3(4)

VREF-/VeREF-(4)(5)

N/A

(1)

X = Don

't care

(2)

N/A = Not available or not applicable

(3)

Default after reset (PUC/POR)

(4)

Setting the ADC10AE.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(5)

An applied voltage is used as negative reference if bit SREF3 in register ADC10CTL0 is set.

MSP430F2012IN 数据表(PDF) 58 Page - Texas Instruments

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