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MSP430F2012IN 数据表(PDF) 60 Page - Texas Instruments |
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MSP430F2012IN 数据表(HTML) 60 Page - Texas Instruments |
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60 / 91 page ![]() Bus Keeper EN Direction 0: Input 1: Output 1 0 P1DIR.5 P1IN.5 P1IRQ.5 D EN Module X IN 1 0 Module X OUT P1OUT.5 Interrupt Edge Select Q EN Set P1SEL.5 P1IES.5 P1IFG.5 P1IE.5 P1.5/TA0/SCLK/A5/TMS 1 0 DVSS DVCC P1REN.5 P1SEL.5 USIPE5 USI Module Direction 1 To JTAG From JTAG ADC10AE.5 Pad Logic INCHx = 5 A5 MSP430F20x3 MSP430F20x2 MSP430F20x1 SLAS491G – AUGUST 2005 – REVISED APRIL 2011 www.ti.com Port P1 (P1.5) Pin Schematics, MSP430F20x2 60 Copyright © 2005–2011, Texas Instruments Incorporated |
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